There is a current need for analog-to-digital (A/D) converters having a high bit resolution and data conversion rate in the megahertz range, and having a high degree of stability and precision.
Subranging type A/D converters have been used to take advantage of an inherent capability to do high resolution data conversion with a reduced data processing delay time. Such A/D converters typically include at least two parallel circuit paths; one of which converts the analog signal to a coarse digital word indicative of the most significant bit portion of the converted analog signal, and the second of which converts the analog signal to a fine digital word indicative of the least significant bit portions of the converted analog signal. In the most significant bit, coarse word circuit path, a flash converter or quantizer is utilized to digitize the analog signal. This digitized signal is then reconverted to an analog signal indicative of the most significant bits or coarse word portion of the converted analog signal, and is subtracted from the delayed analog input signal in the least significant bit, or fine word circuit path. The resulting difference analog signal is digitized to form the least significant bits or fine word portion of the digitized input signal. The digitized most significant bits and least significant bits are then combined to produce an output signal.
In a number of applications, such as in radar systems, analog input data is generally gathered over very small intervals of time. A/D converters useful in such applications operate to divide the analog input data into very small data samples, and then convert those data samples into digital numbers for processing purposes in a digital signal processor. Besides very high conversion rates, A/D converters used for such applications must have more bits in the converted digital word, to obtain the desired resolution.
The high speed and high accuracy requirements placed upon A/D converters in various applications typically impose conflicting design demands on the circuit. For example, to satisfy the high speed requirements conventional A/D conversion circuits must typically operate with low impedances and have other operating characteristics which generally limit the accuracy obtainable from such circuits. Though certain components may be constructed in a manner to obtain both high speed and acceptable accuracy, those components are typically expensive and, in any case, serve as the limiting factor in the speed and/or accuracy of the conversion circuit. Moreover, many contemporary converters suffer additional limitations attributable to the use of redundant analog circuitry to generate a series of error correction signals in an effort to provide greater accuracy.
For example, in the circuit disclosed in U.S. Pat. No. 4,342,983, DYNAMICALLY CALIBRATED SUCCESSIVE RANGING A/D CONVERSION SYSTEM AND D/A CONVERTER FOR USE THEREIN, to Weigand, an analog test signal is input to the circuit and an analog correction signal is derived to represent errors corresponding to certain cardinal points in the range of the circuit. The error signal is fed back to offset an analog signal in the converter circuit. Generation of a correction signal corresponding to each of the cardinal points wherein correction is made requires dedicated analog circuitry for the generation of each correction signal. That requirement tends to limit the number of correction points utilized. Moreover, the circuit is limited to corrections in the D/A circuitry, and does not permit compensation for errors in digital quantization.
Other contemporary A/D converters incorporate circuitry operative to compensate for errors in digital quantization, but fail to provide means for providing high accuracy compensation for errors in the D/A circuitry.
The present invention is directed to apparatus and a method for providing an adaptive error correction circuit for digitizing high speed input data, which compensates for errors in all components of the circuit. The present invention avoids the need for extremely high speed, high accuracy components, by segregating high speed data conversion circuitry from high accuracy error correction circuitry. The invention provides for a large number of error correction points without any requirement for redundant analog circuitry.
These and other objects and advantages of the invention are described and illustrated in connection with the exemplary embodiments set forth below.